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RM0008
In connectivity line devices the main system consists of:
Memory and bus architecture
●
Five masters:
–
–
–
Cortex?-M3 core DCode bus (D-bus) and System bus (S-bus)
GP-DMA1 & 2 (general-purpose DMA)
Ethernet DMA
●
Three slaves:
–
–
–
Internal SRAM
Internal Flash memory
AHB to APB bridges (AHB2APBx), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 2 :
Figure 2.
System architecture in connectivity line devices
ICode
DCode
FLITF
Flash
Cortex-M3
Sys tem
SRAM
DMA1
DMA
Reset & clock
control (RCC)
Ch.1
Ch.2
AHB system bus
Bridge 2
Ch.7
Bridge 1
APB2
APB 1
ADC1
GPIOC
DAC
SPI3/I2S
ADC2
GPIOD
PWR SPI2/I2S
DMA2
DMA request
USART1
SPI1
TIM1
GPIOA
GPIOB
GPIOE
EXTI
AFIO
BKP
CAN1
CAN2
I2C2
I2C1
IWDG
WWDG
RTC
TIM7
TIM6
UART5
UART4
TIM5
TIM4
Ch.1
USART3 TIM3
USART2 TIM2
Ch.2
DMA request
Ch.5
Ethernet MAC
USB OTG FS
ai15810
ICode bus
This bus connects the Instruction bus of the Cortex?-M3 core to the Flash memory
instruction interface. Prefetching is performed on this bus.
Doc ID 13902 Rev 9
39/995
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